Transistor Characteristics of Semi Analytical 14 nm Gate Length Bi-GNMOS’s

Publication Issue: 
Volume 38, Issue 1, 2017
Page No: 
Date Received: 
Friday, November 11, 2016
Authors' Name: 
Noor Faizah Zainul Abidin
Dr. Ibrahim bin Ahmad
Dr. Ker Pin Jern
Dr. P. Susthitha Menon
Authors' Affiliation and Address: 
Centre for Micro and Nano Engineering (CeMNE) Universiti Tenaga Nasional (UNITEN) 43009 Kajang, Selangor, Malaysia
Institute of Microengineering and Nanoelectronics (IMEN) Universiti Kebangsaan Malaysia (UKM) 43600 Bangi, Selagor, Malaysia
Bilayer graphene shows a remarkable physical property where its bandgap is tunable if an electric field is applied perpendicularly to the plane. This has overcome the problem of a single layer graphene in which the bandgap is difficult to be tuned. While researchers are showing interest in other transistor architecture such as FinFET and Trigate Field Effect Transistor, this paper has opted to explore on the enhancement of a conventional planar design by utilizing the graphene layers for which this is the first high performance planar transistor at 14-nm gate length. The development of a planar 14nm bilayer graphene top-gated n-type transistor was virtually fabricated and analyzed using SILVACO TCADS Tools. The model of bilayer grapheme transistor developed using SILVACO is a semi analytical model and it is suitable for exploring the process parameter in order to design a device structure with promising transistor performance. Our device, based on the effective mass calculation and ballistic transport assumption takes into account all relevant physical properties of bilayer graphene. The performance of the device was studied comprehensively and the performance was compared with that of the High-K/metal gate transistor. The device’s simulation was carried out at fixed VTH = ±0.230 V as guided by ITRS 2013. The results in the attainment of optimum VTH show a better performance than High-K/metal gate transistor with ION = 116.226 μA/um, IOFF = 0.128636 nA/um, DIBL=246.408 mV/V and SS = 134.652 mV/dec. Furthermore, this work highlighted the challenges of utilizing graphene-based devices for high performance digital applications and provided an optimized platform for future Graphene NMOS device enhancement.
PDF icon JFM2017_V38No1_010026.pdf594.96 KB